Zum Ram Idle Timer:
DRAM Idle Timer
Common Options : 0T, 8T, 16T, 64T, Infinite, Auto
Quick Review
This BIOS feature sets the number of idle cycles that is allowed before the memory controller forces such open pages to close and precharge.
The premise behind this BIOS feature is the concept of temporal locality. According to this concept, the longer the open page is left idle, the less likely it will be accessed again before it needs to be precharged. Therefore, it would be better to prematurely close and precharge the page so that it can be opened quickly when a data request comes along.
It can be set to a variety of clock cycles from 0T to 64T. This sets the number of clock cycles the open pages are allowed to idle before they are closed and precharged. There\'s also an Infinite option as well as an Auto option.
If you select 0 Cycle, then the memory controller will immediately precharge the open pages as soon as there\'s an idle cycle.
If you select Infinite, the memory controller will never precharge the open pages prematurely. The open pages will be left activated until they have to be precharged.
If you select Auto, the memory controller will use the manufacturer\'s preset default setting.
Most manufacturers use a default value of 8T which allows the memory controller to precharge the open pages once eight idle cycles have passed.
For general desktop use, it is recommended that you choose the Infinite option so that precharging can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.
For applications (i.e. servers) that perform a lot of random accesses, it is advisable that you select 0T as subsequent data requests would most likely be fulfilled by other pages. Closing open pages to precharge will prepare those pages for the next data request that hits them. There\'s also the added benefit of increased data integrity due to more frequent refreshes.
Zur Bank Cycle Time:
The bank cycle time (tRAS) specifies the number of clock cycles needed after a bank active command before a precharge can occur. In other words, after a page has been opened, it needs to stay open a minimum amount of time before it can be closed again. tRC specifies the minimum cycle time until the same bank can be reactivated. Since a precharge has a latency of 2 or 3 cycles, Trc is the sum of tRAS and RAS precharge time (tRP).
Die erste Antwort ist aus \"The Definitive BIOS Optimization Guide\"
http://www.rojakpot.com/default.aspx?location=9Die zweite von: \"LostCircuits BIOS guide
What You Never Wanted To Know But Constantly Dared To Ask\" :D
http://www.lostcircuits.com/advice/bios2/7.shtml(noch aus SDRAM-Zeiten, aber das Prinzip wird sich ja nicht verändert haben.)
